1. Field of the Invention
The present invention relates to a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure.
2. Discussion of Related Art
In current SoC design, a platform-based design method is used to solve a productivity problem in chip design and increase reuse of intellectual property (IP). In order to construct SoC platforms, data communication architectures of various forms serving as frames of the platforms have been disclosed. A SoC platform is a basic template for SoC design, having a structure in which a processor, a memory and peripherals are coupled to an on-chip bus. An AMBA bus architecture, which is the most typical on-chip bus architecture, includes Advanced System Bus (ASB)/Advanced Peripheral Bus (APB) using a single bus architecture, multi-layer Advanced High Performance Bus (AHB)/APB using AHB and a multi-bus architecture, and so on.
FIG. 1A illustrates a SoC platform having a single bus architecture in which an ASB/AHB system bus 110, which is an on-chip bus, connects a processor 100 having 4 masters with a slave hardware module 130 such as IP or a shared memory. The on-chip bus architecture having the single bus has a drawback in that when a master M0 uses the AHB bus, another master M1 cannot use the AHB bus, data communication is delayed, and thus overall performance is lowered.
In order to solve this problem, a SoC platform having a multi-bus architecture as illustrated in FIG. 1B has been provided. The architecture uses a busmatrix 150 serving as a switch for connecting each AHB bus with another AHB bus. While a master M0 in one unit block 140 transfers data to a slave S1, a master M2 in another unit block 160 can transfer data to a slave S2, and a master M3 in yet another unit block 170 can transfer data to a slave S4.
However, while the master M0 in unit block 140 uses an AHB1 bus and an AHB3 bus to transfer data to the slave S4 in unit block 170, a master M1 and master M3 cannot use the AHB1 bus and the AHB3 bus. Therefore, data delay is caused in the multi-bus architecture and throughput is restricted. Consequently, in order to solve this problem, a data communication architecture and data transfer method appropriate to a multi-processor SoC system comprising a plurality of processors are in demand.
To this end, an on-chip network architecture has been suggested that uses an M×N crossbar switch used in computer communication as a SoC bus architecture. By using a crossbar switch instead of an on-chip bus, parallel data communication is allowed, so that system performance can be improved by transferring data at high speed without data transfer delay.
FIG. 2 illustrates a multi-processor SoC platform architecture in which 4 masters M0 201 to M3 204 and 4 slaves S0 206 to S3 209 are connected by four 4×1 multiplexers. A controller 205 manages functions of an arbiter for mediating requests of the masters, an address decoder for connecting masters with slaves, and so on. Therefore, data is not Simultaneously transferred from masters M0 201 and M1 202 to the slave S0 206 instead, transfer is performed by the arbiter in order of priority of masters, and a slave is selected by the address decoder. In this architecture, simultaneous data transfer from M0 to S0 and from M1 to S3 is possible.
There are transfer paths from M0 201 to all the slaves S0 206 to S3 209, and data is transferred through one multiplexer. In addition, data transfer from the slave S0 206 to all of the masters M0 201 to M3 204 is possible. The multiplexers used in the crossbar switch are master M×1 multiplexers and there should be as many of them as there are slaves S. In this architecture including 4 masters and 4 slaves, eight 4×1 multiplexers are needed. Also, there is a data path from each master to each slave, and data transfer from a master to a slave is possible through only one multiplexer.
In the illustrated architecture, high-speed parallel data transfer is possible using a crossbar switch. However, when the number of masters or slaves increases, the multiplexer structure of each master or slave must be changed. For example, when one master is added, the 4×1 multiplexers 210 to 213 connected to each slave must be changed into 5×1 multiplexers. In addition, the number of control bits transferred from the controller to the multiplexers increases from 2 bits to 3 bits, and thus the controller becomes complicated. Thus, increase in the number of masters or slaves, i.e., expandability, is restricted. Consequently, in this architecture frequently used in on-chip network architectures, high-speed data transfer is possible, but it is difficult to add masters/slaves.